1. Field of the Invention
The present invention relates to a semiconductor memory device and, more particularly, to a semiconductor memory device having a circuit for automatically checking and correcting an error of data output from a sense amplifying circuit, hereinafter referred to as an S/A circuit, provided for a memory cell array.
2. Description of the Related Art
Referring to an example of a memory, for example, an electrically erasable and programmable read only memory (EEPROM), a possible number of times of the repetition of re-writing is defined as one of the important characteristics of the EEPROM. The possible number of times thereof is defined from a viewpoint in that a manufacturer guarantees a quality of the device for a user. However, when the re-writing is frequently repeated, there is a possibility that a memory cell becomes non-functional due to a crystallinity of semiconductor constituting the memory cell, a deterioration in a tunnel insulation film and the like, particles of dust, an unsatisfactory patterning, or the like. As for most of the memories which become non-functional due to these causes, the ratio of the non-functional bits to all bits, e.g., 64K or 65,536 bits, is 1 to 10 bits and extremely small. That is, it lies in the accidental failure region in the classification of failures.
To cope with the problem, Seeq Tech. Co. proposed a device in 1984 in which an error check and correct (ECC) circuit together with a memory is mounted on a chip (ISSCC 84, THAM 10.4). In the ECC circuit, when an information data is written into cells, a check data is generated based on a combination of certain bits of the information data. Next, when the information data written into the cells is read out via an S/A circuit, the check and correction of the information data is carried out based on a combination of certain bits of the check data and information data. That is, where a certain bit of the information data is wrong, the logical level of the wrong bit is inverted to the right level. Thus, according to the ECC circuit, even if a cell of one bit among one word becomes non-functional, a right output signal can be read out.
In the EEPROM device having the ECC circuit, however, when a margin between logical levels "1" and "0" of a certain cell is decreased due to the deterioration in the tunnel insulation film and, accordingly, a transition of level of the output of a corresponding S/A is delayed, the ECC circuit cannot quickly effect its check and correct operation. Therefore, a problem occurs in that the ECC circuit once effects a correct operation for a "right" logical level of a certain cell and, after a while, cancels the correct operation. During the operation, the logical level of the output signal of the ECC circuit transiently changes from "1" level (or "0" level) to "0" level (or "1" level) and, then, returns to "1" level (or "0" level). That is, a spike-like transient error, hereinafter referred to as a hazard, appears in the output signal of the ECC circuit. This means that the correction of error data by the ECC circuit, hereinafter referred to as an ECC relief, cannot be perfectly carried out, and is not preferable from a viewpoint of a high-accurate reading of data.
Also, where the aforementioned margin between logical levels "1" and "0" of a certain cell is decreased below a certain level, the output signal of the corresponding S/A circuit is oscillated in level in the transition region between "1" and "0". As a result, the ECC circuit effects a mis-operation. That is, the perfect ECC relief cannot be realized.
Furthermore, the above problem is not characteristic to a non-volatile memory such as an EEPROM in which charges leak from a cell or cells due to the deterioration in the cells as times go by, but can happen to a volatile memory in which the leak in a cell does not occur, e.g., a dynamic random access memory (DRAM), a static RAM (SRAM) and the like. That is, a problem arises in that, due to the non-uniformity in operation speed among each of the S/A circuits in the reading operation, a time at which a logical level of each bit of the data to be read out is settled does not coincide. Thus, the ECC circuit effects a mis-operation resulting in the appearance of the hazard in the output signal thereof.